Senior FPGA Developer (SystemVerilog)

<div class="content-intro"><p><img src="https://i.imgur.com/XN94Hg4.png" alt="" width="900" style="max-width: 100%;"></p> <p>&nbsp;</p></div><p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Role</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}">&nbsp;</span></strong></p> <p><span data-contrast="auto">The Senior FPGA Developer&nbsp;will be a member of the core team building the&nbsp;Quantum Key Distribution&nbsp;system. The focus is end</span><span data-contrast="auto">‑</span><span data-contrast="auto">to</span><span data-contrast="auto">‑</span><span data-contrast="auto">end RTL ownership on AMD/Xilinx (Artix</span><span data-contrast="auto">‑</span><span data-contrast="auto">7,&nbsp;Kintex&nbsp;UltraScale): architect,&nbsp;implement,&nbsp;verify, and close timing on high</span><span data-contrast="auto">‑</span><span data-contrast="auto">rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and&nbsp;mentors&nbsp;a junior engineer.</span><span data-ccp-props="{}">&nbsp;</span></p> <p><span data-contrast="auto">The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring</span><span data-contrast="auto">‑</span><span data-contrast="auto">up, and deliver reproducible, versioned bitstreams.</span><span data-ccp-props="{}">&nbsp;</span></p> <p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Responsibilities</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}">&nbsp;</span></strong></p> <p><span data-contrast="auto">The Senior FPGA Developer should expect to work&nbsp;in&nbsp;the following activities.</span><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">RTL architecture, interfaces, and&nbsp;rather high-speed&nbsp;datapaths</span> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Owning SystemVerilog RTL architecture/implementation for Artix<span data-contrast="auto">‑</span><span data-contrast="auto">7 and&nbsp;Kintex&nbsp;UltraScale&nbsp;(SystemVerilog,&nbsp;Vivado)</span></li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third<span data-contrast="auto">‑</span><span data-contrast="auto">party MAC/PCS IP</span></li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low<span data-contrast="auto">‑</span><span data-contrast="auto">level protocols&nbsp;—&nbsp;</span> <span data-contrast="auto">and bridging them to high</span><span data-contrast="auto">‑</span><span data-contrast="auto">throughput interfaces (DDR/PCIe)</span></li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Defining clear AXI/AXI<span data-contrast="auto">‑</span><span data-contrast="auto">Stream boundaries and register maps for SW/FW integration</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Constraints, timing closure, and&nbsp;floorplanning</span> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Authoring and maintaining XDC constraints (clocks, I/O, exceptions); achieving consistent timing closure across corners</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Applying practical floorplanning (pblocks, placement guidance) and CDC methodology; analyzing reports and iterating for margin<span data-ccp-props="{}">&nbsp;</span></li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Verification and CI</span> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Establishing a professional verification environment with ModelSim/Questa; developing self<span data-contrast="auto">‑</span><span data-contrast="auto">checking testbenches and regression suites; integrating Python/cocotb&nbsp;co</span><span data-contrast="auto">‑</span><span data-contrast="auto">simulation with software harnesses/mocks; defining coverage goals (OSVVM/UVM as&nbsp;appropriate)</span></li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Building CI for lint/sim/synth/impl; archiving reports/bitstreams; automating regressions (including cocotb) and basic HW<span data-contrast="auto">‑</span><span data-contrast="auto">in</span><span data-contrast="auto">‑</span><span data-contrast="auto">the</span><span data-contrast="auto">‑</span><span data-contrast="auto">loop smoke tests</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Bring-up, debug, and releases</span> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Board bring-up and debug using ILA/logic analyzers; link training, memory calib, and protocol bring-up</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Owning bitstream packaging, versioning, and release notes; ensuring reproducible builds and traceable artifacts<span data-ccp-props="{}">&nbsp;</span></li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Cross-team&nbsp;collaboration and mentoring</span> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Driving system integration with SW/FW: register/driver contracts, throughput/latency budgets, HIL</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Mentoring a junior engineer; codifying style guides, reviews, and design documentation<span data-ccp-props="{}">&nbsp;</span></li> </ul> </li> </ul> <p>&nbsp;</p> <p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 2">The Requirements</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":160,"335559739":80}">&nbsp;</span></strong></p> <p><span data-contrast="auto">The Senior FPGA Developer is expected to have the following qualifications and experience.</span><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="13" data-aria-level="1"><span data-contrast="auto">5+ years production FPGA on AMD/Xilinx; expert&nbsp;SystemVerilog&nbsp;RTL</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="14" data-aria-level="1"><span data-contrast="auto">Demonstrated mentoring of junior engineers</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="15" data-aria-level="1"><span data-contrast="auto">Strong constraints/timing (XDC), CDC/reset, and practical&nbsp;floorplanning; consistent timing closure</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="16" data-aria-level="1"><span data-contrast="auto">Hands</span><span data-contrast="auto">‑</span><span data-contrast="auto">on DDR3/DDR4, PCIe endpoints/DMA, Ethernet/SFP; integrating/evaluating third</span><span data-contrast="auto">‑</span><span data-contrast=